1. Field of the Invention
This invention generally relates to signal phase detection and tracking and, more particularly, to a system and method to optimize an early/late phase detector by correcting for jitter.
2. Description of the Related Art
FIG. 1 is a diagram illustrating a signal recovered from a binary symmetric, non-dispersive channel in the presence of noise (prior art). Conventionally, the signal is filtered with a transfer function matched to the signaling waveform (in this case a one unit step) and thresholded at the voltage level most likely to yield the transmitted bit. To recover the transmitted information, a hard decision must be made on the value of the received bit.
As a function of the filtering process, and sometimes as a result of the transmission process, pulse spreading occurs. That is, the energy associated with a bit spreads to neighboring bits. For small degrees of spreading these effects of this can be limited to the nearest neighbors with modest degradation in performance.
Three basic types of pulse spreading exist. The first possibility is that both the neighboring bits are a zero (no neighboring bits are a one). The second possibility is that only one of the neighboring bits (either the preceding or subsequent bit) is a one. Alternately stated, only one of the neighboring bits is a zero. The third possibility is that both neighboring bits are one.
FIG. 2 is a diagram illustrating received waveforms that are distorted in response to the inter-symbol interference resulting from energy dispersion (prior art). The value at the output of the filter varies with each bit, and is essentially a random process, due to the non-deterministic nature of the information, and scrambling that is often used in the transmission of data streams. However, received bits can be characterized with probability density functions (PDFs), as shown. Without knowledge of the neighboring bits, a single probability density function could be extracted that represents the random behavior of the input over all conditions and all sequences. However, conditional probability density functions can be defined for the three cases mentioned above. Namely, probability density functions can be defined for the cases where there are zero neighboring ones, only one neighboring one, and two neighboring ones.
The degree of dispersion exhibited by a channel, and hence the separation of the conditional probability density functions, varies in response to a number of fixed and variable factors. Effective dispersion mitigation techniques must therefore be optimized to the channel and somewhat adaptive to changes in the channel due to aging, temperature changes, reconfiguration, and other possible influences.
The above-mentioned problems are compounded if the receiver must recover the clock from the incoming data stream. That is, ISI on the received data may cause the phase detector to adjust the phase in the wrong direction if all possible ISI patterns are treated equally. Clock jitter results from the inability of a phase detector to properly lock or track phase, which becomes another source of increased bit error rate (BER).
If the bit value decision process could be made using the knowledge of the decision made on the preceding decoded bit, or with a measurement of preceding and subsequent decoded bits, then the corresponding probability density function could be selected to make a more accurate decision on the current bit decision. Such a process would require that the bits be converted from analog to digital information. However, it is not practical to perform an analog-to-digital (A/D) conversion at high serial stream data rates.
Another problem is jitter in the received data, which randomly shifts the rising and falling edges of the data along the time axis, making the ideal sampling time difficult to determine. The jitter may be a result of channel or transmission line degradations for example. One of the primary non-linearities associated with a digital phase detector comes from untracked input jitter distribution.
Conventionally, an early-late phase detector uses two clocks, an I-clock and a Q-clock, 90 degree apart in phase. The fixed phase between I-clock and Q-clock assumes that there is low input jitter, so the jitter's effect can be ignored. Ideally however, the phase difference between I-clock and Q-clock should track the jitter to minimize BER.
Further, there is a latency associated with processing of digital signals. Since the latency of a digital phase detector and the feedback loop used in a clock and data recovery (CDR) device determines the performance of CDR locking, tracking, and jitter, the feedback design must keep the latency as low as possible. The inherent latency of conventional digital circuitry limits the use of purely digital oscillator circuitry to relatively low frequencies.
It would be advantageous if phase detector signal tracking could be improved using ISI pattern weighting and jitter tracking. It would be advantageous if the pattern weighting and jitter tracking could be performed in the digital domain to save power.